SN74ALVC7803-25DLR

SN74ALVC7803-25DLR
Mfr. #:
SN74ALVC7803-25DLR
Сипаттама:
FIFO 512 X 18 CLOCKED FIFO
Өміршеңдік кезең:
Осы өндірушіден жаңа.
Деректер тізімі:
SN74ALVC7803-25DLR Деректер тізімі
Жеткізу:
DHL FedEx Ups TNT EMS
Төлем:
T/T Paypal Visa MoneyGram Western Union
ECAD Model:
Көбірек ақпарат:
SN74ALVC7803-25DLR Көбірек ақпарат SN74ALVC7803-25DLR Product Details
Өнім атрибуты
Төлсипат мәні
Өндіруші:
Texas Instruments
Өнім санаты:
FIFO
Пакет/қорап:
SSOP-56
Бренд:
Texas Instruments
Орнату стилі:
SMD/SMT
Жұмыс кернеуі:
3 V to 3.6 V
Өнім түрі:
FIFO
Ішкі санат:
Жад және деректерді сақтау
Бірлік салмағы:
0.024508 oz
Tags
SN74ALVC7803-2, SN74ALVC7803, SN74ALVC780, SN74ALVC7, SN74ALVC, SN74ALV, SN74AL, SN74A, SN74, SN7
Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
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Email: [email protected]

Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***et
FIFO Mem Sync Dual Width Uni-Dir 512 x 18 56-Pin SSOP T/R
***i-Key Marketplace
FIFO, 512X18, 15NS, SYNCHRONOUS
***as Instruments
The SN74ALVC7803 FIFO is suited for buffering asynchronous data paths at 50-MHz clock rates and 13-ns access times and is designed for 3-V to 3.6-V VCC operation. The 56-pin shrink small-outline (DL) package offers greatly reduced board space over DIP, PLCC, and conventional SOIC packages. Two devices can be configured for bidirectional data buffering without additional logic. The write clock (WRTCLK) and read clock (RDCLK) should be free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, is low, and input ready (IR) is high. Data is read from memory on the rising edge of RDCLK when ,, and are low and output ready (OR) is high. The first word written to memory is clocked through to the output buffer regardless of the ,, and levels. The OR flag indicates that valid data is present on the output buffer. The FIFO can be reset asynchronously to WRTCLK and RDCLK. must be asserted while at least four WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset upon power up.
Бөлім № Сипаттама Қор Бағасы
SN74ALVC7803-25DLR
DISTI # SN74ALVC7803-25DLR-ND
IC MEMORY FIFO 512X18 56-SSOP
RoHS: Compliant
Min Qty: 1000
Container: Tape & Reel (TR)
Limited Supply - Call
    SN74ALVC7803-25DLR
    DISTI # N/A
    FIFO 512 X 18 CLOCKED FIFO0
      SN74ALVC7803-25DLRFIFO, 512X18, 15ns, Synchronous, CMOS, PDSO56
      RoHS: Compliant
      1000
      • 1000:$6.9300
      • 500:$7.3000
      • 100:$7.6000
      • 25:$7.9300
      • 1:$8.5300
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      OMO.#: OMO-SN74ALVC7806-25DL-TEXAS-INSTRUMENTS

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      Қол жетімділік
      Қор:
      Available
      Тапсырыс бойынша:
      3500
      Саны енгізіңіз:
      SN74ALVC7803-25DLR ағымдағы бағасы тек анықтама үшін берілген, егер сіз ең жақсы бағаны алғыңыз келсе, сату тобымызға [email protected] мекенжайына сұрауды немесе тікелей электрондық поштаны жіберіңіз.
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