AD9557/8 Clock Multiplier

By Analog Devices Inc 19

AD9557/8 Clock Multiplier

Analog Devices' AD9557 is a low loop bandwidth clock multiplier that provides jitter cleanup and synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9557 generates an output clock synchronized to one or two external input references. The digital PLL allows for reduction of input time jitter or phase noise associated with the external references. The digitally-controlled loop and holdover circuitry of the AD9557 continuously generates a low jitter output clock even when all reference inputs have failed.

The AD9558 provides synchronization for many systems, including synchronous Ethernet (SyncE) and synchronous optical networks (SONET/SDH). The AD9558 generates an output clock synchronized to one of up to four external input references. The digital PLL allows for reduction of input time jitter or phase noise associated with the external references. The AD9558 continuously generates a clean (low jitter), valid output clock even when all references have failed by means of a digitally controlled loop and holdover circuitry.

Applications
  • Network synchronization including synchronous Ethernet and SDH to OTN mapping / de-mapping
  • Stratum 3 holdover, jitter cleanup, and phase transient control
  • SONET/SDH clocks up to OC-192, including FEC
  • Wireless base station controllers
  • Cleanup of reference clock jitter
  • Cable infrastructure
  • Data communications

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