HCSL Buffers

By IDT, Integrated Device Technology Inc 204

HCSL Buffers

IDT's 85102I is a low-skew, 1-to-2 differential/LVCMOS-to-HCSL fanout buffer. The 85102I has two selectable clock inputs. The differential input supports LVPECL, LVDS, HSTL, SSTL and HCSL input levels. The single-ended input supports LVCMOS/LVTTL signal levels. The device is supplied by 3.3 V. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin.

The 85104I is a low skew, 1-to-4 differential/LVCMOS-to-HCSL fanout buffer. The 85104I has two selectable clock inputs, the differential input supports LVPECL, LVDS, HSTL, SSTL and HCSL input levels. The single-ended input supports LVCMOS/LVTTL signal levels. The device is supplied by 3.3 V. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin.

The ICS85108I is a low skew, high performance 1-to-8 differential-to-0.7 V HCSL clock distribution chip and a member of the HiPerClockS™ family of high performance clock solutions from IDT. The ICS85108I CLK, nCLK pair can accept most differential input levels and translates them to 3.3 V HCSL output levels. The ICS85108I provides a low power, low noise, low skew, point-to-point solution for distributing HCSL clock signals. Guaranteed output and part-to-part skew specifications make the ICS85108I ideal for those applications demanding well defined performance and repeatability.


Жаңа өнімдер:

85102AGILF85104AGILF85108AGILF

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